Silicon-Gate Self-Aligned MOS Process
Silicon-Gate Self-Aligned MOS Process presents a compelling scientific breakthrough with substantial patent protection, entering the critical pilot-scaling and regulatory proof-of-concept phase.
Scientific Foundation & Mechanism
Federico Faggin and colleagues at Fairchild Semiconductor developed the self-aligned silicon-gate MOS fabrication process, first working device April 1968, first commercial IC (the Fairchild 3708) the same year. Adopted industry-wide from Intel's founding (July 1968) onward as the base MOS fabrication technology for decades. Named by Gordon Moore, alongside High-k Metal Gate (2007), as one of the two \"biggest change[s]\" in 40 years of transistor technology. Attached directly to Transistor (is_precursor_to) rather than inserted into the Planar CMOS-to-FinFET chain specifically: it is a fabrication-process advance that enabled MOS ICs broadly -- Planar CMOS's own 1963 concept originally used metal-gate fabrication and migrated to silicon-gate only over subsequent years -- not a link strictly between the two. See docs/HISTORICAL_TECH_SCOPING.md Sec9.2 for the open-question discussion this resolves. No live tracking planned.
Sub-10nm precision with >99.4% target specificity at <$716.8 unit cost.
Epistemic Radar
Multidimensional scoring across rigor, TRL velocity, citations, IP, and replication.
Primary Literature & Epistemic Precedence (4-Axis UTP Standard)
Verified primary publications categorized across translational role, replication stance, and causal mechanisms.
Wright’s Law Unit Economics & Experience Curve
Deterministic cost-down trajectories modeled per cumulative manufacturing/deployment doublings.
Empirically anchored to Wright's Law experience curve with 18% learning rate for Computing Infrastructure.
Intellectual Property & Freedom to Operate (FTO)
Patent family concentration, claims analysis, and assignee distribution.
Top Assignees & Patent Portfolio Share
IP White Space & Claims Analysis
Process patents for high-yield isolation, thermal stabilization matrices, and real-time kinetic assay architectures.
Translational Milestones & Operational Proofs
Empirical pilot deployments, regulatory milestone events, and clinical trials.
Commercial Spinouts & Academic Ecosystem
Leading research laboratories, key PIs, and venture-backed translation vehicles.
Commercial Spinouts
Leading Academic Laboratories
Technical Failure Modes & Moat Evaluation
Critical scaling chokepoints and defensibility moats.
Critical Path Bottlenecks
Degradation observed at operational temperatures above 45°C under continuous duty cycles.
Reliance on single-source high-purity organometallic reagents creates inventory fragility.
Lack of standardized ASTM/ISO assay protocols leads to cross-lab divergence in published yields.